** SimpleRISC ** is an optional coursework of one of my favorite class -- High-Performance Computer Systems, lectured by Weiwu Hu, the chief engineer of Loongson.
Though very simple with the absence of the executing out-of-order feature and the memory access feature and a very simple ISA, this simple "CPU" implementation employs a full featured in-order pipeline, which is very useful in understanding the essence of the superscalar feature of modern CPU micro-architecture design.
- RISC
- 16-bit width instructions and data
- 8 GPR (general purpose registers), #0 GPR is always zero
- one fixed-point ALU
- Register Type
- Immediate Type
| I-Type | OP(4) | RD(3) | RS(3) | Immediate | |
| R-Type | OP(4) | RD(3) | RS1(3) | RS2(3) | OPX(3) |
| ADD | 0001 | rd | rs1 | rs2 | 000 |
| SUB | 0010 | rd | rs1 | rs2 | 000 |
| AND | 0011 | rd | rs1 | rs2 | 000 |
| OR | 0100 | rd | rs1 | rs2 | 000 |
| SR | 0111 | rd | rs1 | rs2 | 000 |
| NOT | 0101 | rd | rs1 | rs2 | 000 |
| SRU | 1000 | rd | rs1 | rs2 | 000 |
| SL | 0110 | rd | rs1 | rs2 | 000 |
| BZ | 1100 | 000 | rs1 | offset | |
| LD | 1010 | rd | base | offset | |
| ST | 1011 | rd | base | offset | |
| ADDI | 1001 | rd | rs1 | imm | |
| BGT | 1100 | 001 | rs1 | offset | |
| BLE | 1100 | 010 | rs1 | offset | |
After some optimization, the final data path is illustrated below.
** Note: All the materials are from my class "High-Performance Computer Systems", and all rights reserved. **
This is just a simple course work at the very begining of the course, and the whole course is far more complex than this small course work.