浩 (huangliwood)

huangliwood

Geek Repo

Location:shenzhen university

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's repositories

Bingo

The source code of "Bingo Spatial Data Prefetcher" paper, which is accepted in HPCA 2019.

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env-scripts

Scripts for XiangShan

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SnaTCHer

[CVPR 2021] Few-shot Open-set Recognition by Transformation Consistency

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ChampSim

ChampSim repository

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CoupledL2

Open-source non-blocking L2 cache

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difftest

Co-simulation framework for Xiangshan

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HuanCun

Open-source high-performance non-blocking cache

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Pythia

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

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XiangShan

Open-source high-performance RISC-V processor

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Algorithms-Scala

All Algorithms implemented in Scala

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blog-zinnia

Simple yet powerful and really extendable application for managing a blog within your Django Web site.

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cloudsim

CloudSim: A Framework For Modeling And Simulation Of Cloud Computing Infrastructures And Services

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DjangoBlog

🍺基于Django的博客系统

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docker_image_pusher

使用Github Action将国外的Docker镜像转存到阿里云私有仓库,供国内服务器使用,免费易用

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gem5_data_proc

data preprocessing scripts for gem5 output

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izone

一个基于Django的博客项目,也可以当做一个文档管理网站使用,自带评论、定时任务等功能,界面简约而不简单

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lede

Lean's OpenWrt source

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openwrt

Lienol's Modified OpenWrt source

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OpenWRT-1

自动编译OpenWRT

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OpenWrt-SSRPLUS

包含ShadowsocksR Plus+、Passwall和Clash/OpenClash IPK文件的GitHub云编译(x86_64架构专用,包含依赖)。最后一个编译的版本已经支持Xray。详见Release页面。

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pyuvm

The UVM written in Python

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Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

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riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

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riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

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rocket-chip

Rocket Chip Generator

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SZUThesisLatest

毕业论文

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