hossein1387

BARVINN

BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

MVU

Neural Network accelerator powered by MVUs and RISC-V.

random_hw_experiments

nn_from_scratch

hossein1387.github.io

Personal Website

GOL

mojo

The Mojo Programming Language

awesome-semiconductor-startups

List of awesome semiconductor startups

pito_riscv

A Barrel design of RV32I

fusesoc-cores

FuseSoC standard core library

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux. Refer to https://github.com/openhwgroup/cva6

openpiton

The OpenPiton Platform

MLExperiments

My experiments with ML tools

tinytapeout-verilog-test

Simple project to test Tinytapeout

wokwi-verilog-gds-test

common_cells

Common SystemVerilog components

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

IFT6135

Assignments and Project for IFT6135 REPRESENTATION LEARNING (Universite De Montreal)

U-Net-Fixed-Point-Quantization-for-Medical-Image-Segmentation

Repository containing code for "U-Net Fixed-Point Quantization for Medical Image Segmentation" paper at MICCAI2019

al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

MVU_Codegen

ReCU

Pytorch implementation of our paper accepted by ICCV 2021 -- ReCU: Reviving the Dead Weights in Binary Neural Networks http://arxiv.org/abs/2103.12369

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.9, working as a coprocessor to CORE-V's CVA6 core

TestSV

twitchcore

It's a core. Made on Twitch.

onnx-surgery

miraliahmadli

IntegerLenet

APoT_Quantization

PyTorch implementation for the APoT quantization (ICLR 2020)

ssd.pytorch

A PyTorch Implementation of Single Shot MultiBox Detector