hjzboss

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

nudt_thesis

NUDT硕士博士毕业论文latex模板

ctags

A maintained ctags implementation

llvm-project

PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-vectorized-benchmark-suite

RiVEC Bencmark Suite

ChampSim

ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

RISC-V-Vector

Vector processor for RISC-V vector ISA

RISC-V-Vector

Vector processor for RISC-V vector ISA

FPGA-LZMA-compressor

FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器，用于通用数据压缩。

rvv-intrinsic-doc

riscv-dv

Random instruction generator for RISC-V processor verification

riscv-isa-sim

Spike, a RISC-V ISA Simulator

ics-workbench-cache

南大PA缓存模拟器实验

ysyxSoC

rocket-chip

Rocket Chip Generator

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

gen_amba_2021

AMBA bus generator including AXI4, AXI3, AHB, and APB

numeric-code-detonator

数字密码引爆器

ysyx-workbench

一生一芯项目仓库

e203_hbirdv2

The Ultra-Low Power RISC-V Core

Quafu

A small SoC with a pipeline 32-bit RISC-V CPU.

AdamRiscv

five-stage-pipeline riscv processor

Online-appointment-registration-platform

基于SpringBoot的网上预约挂号系统。Online appointment registration system based on SpringBoot.

mnist_network

Handwritten digit recognition

NutShell

RISC-V SoC designed by students in UCAS

chisel

fifo

Implementation of synchronous FIFOs and asynchronous FIFOs

RISC-V-32I

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器