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hdl-util / gray-code

Generate a gray code of arbitrary width in SystemVerilog

Home Page:https://purisa.me/blog/arbitrary-width-gray-codes/

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Balanced gray codes

sameer opened this issue · comments

commented

There are methods to produce balanced gray codes: gray codes where the transitions of each bit are evenly distributed across the mapping.

Wikipedia entry describes it better in more concrete mathematical terms.

One algorithm I thought of:

  • Generate a gray code hypercube -- a graph where each vertex is a binary code, and it is connected to all vertices which are 1 bit different (i.e. for bit width of 4, there are 4 adjacent vertices to 0: 1, 2, 4, 8)
  • Find hamiltonian cycles in the graph
  • Check hamiltonian cycles for balance, pick the first balanced one

I read some papers about it, but I don't have an algorithm that would be simple enough to implement in SystemVerilog.