hdl-modules / hdl-modules

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

https://hdl-modules.com

hdl-modules/hdl-modules Issues

Check code quality in a continuous way
Updated 2 months ago
Use 'set_bus_skew' in two-phase CDC constraint
Updated 2 months ago
Make everything except VHDL-2008 compile with quartus
Updated 2 months ago
Investigate if possible to save LUTs in asynchronous FIFO by not converting read pointer
Updated 2 months ago
resync_level without input register never uses set_max_delay constraint
Closed 4 months ago1
Add test that R and B channels are driven invalid when bus is not valid
Closed 8 months ago1
Consider using VUnit's method for removing strobed out AXI-Stream byte lanes
Closed 10 months ago2
Enable PIP and APT caching in CI
Closed a year ago