hattas / fpga-game

VHDL Game for EECE 4740

VHDL Project

Project for EECE 4740, Advanced VHDL Design and FPGAs, Spring 2019

How to generate tile ROM

1. Draw a level map at https://www.pixilart.com with width 20 and height 15
2. Export to png
3. Run the python script to generate the tile map VHDL code
4. Copy into VHDL file