Harvard Architecture, Circuits, and Compilers (harvard-acc)

Harvard Architecture, Circuits, and Compilers

harvard-acc

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Location:Cambridge, MA

Home Page:http://vlsiarch.eecs.harvard.edu/

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Harvard Architecture, Circuits, and Compilers's repositories

gem5-aladdin

End-to-end SoC simulation: integrating the gem5 system simulator with the Aladdin accelerator simulator.

Language:C++License:BSD-3-ClauseStargazers:198Issues:14Issues:37

ALADDIN

A pre-RTL, power-performance model for fixed-function accelerators

Language:C++License:NOASSERTIONStargazers:161Issues:28Issues:32

LLVM-Tracer

An LLVM pass to profile dynamic LLVM IR instructions and runtime values

Language:C++License:NOASSERTIONStargazers:131Issues:25Issues:41

DeepRecSys

http://vlsiarch.eecs.harvard.edu/research/recommendation/

Language:PythonLicense:MITStargazers:123Issues:9Issues:9

smaug

SMAUG: Simulating Machine Learning Applications Using Gem5-Aladdin

Language:C++License:BSD-3-ClauseStargazers:87Issues:7Issues:27

EdgeBERT

HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference

Language:PythonLicense:NOASSERTIONStargazers:39Issues:2Issues:3

FlexASR

FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks

Language:C++License:NOASSERTIONStargazers:36Issues:7Issues:0
Language:PythonStargazers:10Issues:3Issues:0

Trireme

Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration

Language:LLVMStargazers:1Issues:0Issues:0

smaug_docs

Documentation for SMAUG. Autogenerated, do not manually edit.

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