It is an event-driven simulator that accurately simulates a modern phase-chanage memory controller (PCMC). We made every effort to make this architecture resemble the PCM product. Furthermore, the accuracy of the confidential version is verified against RTL trace in SK Hynix, where functional error=3.16% and cycle error=13.6%
Descriptions of important classes in this source code:
Component
: base class for all modulesMemoryControlSystem
: top module of the controllerRequestReceiver
: an interface that receives requests from the hostDataCache
: serves as a data cache for RequestReceiverAITManager
: generates commands to read AIT entries from DRAM subsystemMicroControlUnit
: parent class for firmware algorithms (e.g., wear leveling)ReadModifyWrite
: performs RMW because PCM access granularity > 64BuCMDEngine
: decomposes requests as microcommands (e.g., ACT, PRE, etc.)DataPathUnit
: encode/decode data to/from PCM media
Followings are requirements for the simulator:
- Git
- g++ (version>=4.8, which supports C++11)
- Scons
Steps for executing the simulator:
-
Download PCMCsim
$ git clone https://github.com/harrylee365/pcmcsim_public.git
-
Build PCMCsim in O3 mode with 4 cores (confer
debug
option if O0 is desired)$ cd pcmcsim_public $ scons --build-type=fast -j4
-
Run PCMCsim (for more information, use --help):
$ ./pcmcsim.fast -i ./test_trace/test.input -c ./configs/pcmcsim_base_public.cfg
The simplest configuration example is listed in pcmcsim_public/configs/pcmcsim_base_public.cfg
Two configurations should be noted:
global.system
: determines the system configuration. It can beDRAM
orPCM
. The former simply builds a memory subsystem only instantiatinguCMDEngine
; the latter builds a memory subsystem that incorporates all necessary features for a PCM controllerglobal.ticks_per_cycle
: determines the system frequency. The value '1' means 1 THz frequency. Also, each module can have its on frequency by configuring*.ticks_per_cycle
- Hyokeun Lee hklee@capp.snu.ac.kr
- Seokbo Shim sbshim@capp.snu.ac.kr
- Seungyong Lee sylee@capp.snu.ac.kr
- Hyungsuk Kim kimhs@capp.snu.ac.kr
@inproceedings{PCMCSIM,
author = {Lee, Hyokeun and Kim, Hyungsuk and Lee, Seungyong and Hong, Dosun and Lee, Hyuk-Jae and Kim, Hyun},
title = {PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis},
booktitle = {IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)},
year = {2022}
}
Copyright (c) 2019 Computer Architecture and Paralllel Processing Lab, Seoul National University, Republic of Korea. All rights reserved.
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This project is supported by SK Hynix Inc. (2019-2021)
CONFIDENTIAL codes are REMOVED in this version