haocat / Modexpowering3

a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

ModExpowering3

a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier

what we actually used are:@ Based on the modular exponential project of qinzhou@cs.ucsb.edu; @ Brent Kung Adder; @Karatsuba multiplier

As to the adder module, booth-wallace seems to be a more acceptable choice, but it does not perform well in this project. The max frequency is 222.32Mhz under 100Mhz clk, counter SCA measures are taken seldom consideration, which is the basic poweringladder montgomery.

The gray coding for finite state machine is very useful for decreasing the power. Residue Number System is a powerful choice, but unluckily a harder one.

1. Summary:


2. Architecture of the project:

image

3. Mainmodule ModExpPoweringladder:

image

4. Submodule MonPro:

image

5. Verify via python

6. UVM testbench :

image

About

a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier


Languages

Language:Verilog 45.6%Language:SystemVerilog 23.9%Language:VHDL 17.8%Language:Python 8.5%Language:C 2.2%Language:C++ 1.3%Language:Tcl 0.5%Language:Makefile 0.0%