A tool that help to connect system verilog modules in SoC
This uses modified hdlparse libray (here)[https://github.com/hanhha/hdlparse] to parse IOs and parameters of modules.
A tool that help to connect system verilog modules in SoC
A tool that help to connect system verilog modules in SoC
This uses modified hdlparse libray (here)[https://github.com/hanhha/hdlparse] to parse IOs and parameters of modules.
A tool that help to connect system verilog modules in SoC
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