habibhossam / Design-Spartan6---DSP48A1-using-Vivado

Using Vivado to go through the design flow running elaboration, synthesis, implementation for all the designs making sure that there are no design check errors during the design flow..

The Spartan-6 family offers a high ratio of DSP48A1 slices to logic, making it ideal for math-intensive applications. Design DSP48A1 slice of the spartan6 FPGAs. The testbench for this design can be challenging so use directed test patterns whenever needed to verify the design and either have expected value to compare with in the testbench or check the result from the waveforms. Use do file to run the Questasim flow.