gzyIDE

ParamMod

Parameterized Verilog Modules for many applications

cbp-tage

TAGE implemented in cbp

matmul_csr

CSR based SpMV

riscv-isa-sim

Spike, a RISC-V ISA Simulator

ZYNQ_PL_SDRAM_test

SDRAM Access test from PL logic

xilinx_fpga_template

Xilinx fpga development environment template

SysvDevEnv

Template RTL development environment for SystemVerilog

elfloader_dpi

ELF Loader DPI for systemverilog simulation environment

gzyIDE

Config files for my GitHub profile.

rust_perceptron

Rust practice

datapath

datapath modules with chisel

fputil

perceptron

verilog implementation of perceptron