posedgeyx's repositories
80x86
80186 compatible SystemVerilog CPU core and FPGA reference design
AHB-lite-Verification-in-SystemVerilog
EE-599f SoC SystemVerilog Final Project
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cocotb-bus
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
cocotb-coverage
Functional Coverage and Constrained Randomization Extensions for Cocotb
core_ftdi_bridge
FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
cores
Various HDL (Verilog) IP Cores
FPGA-DAC-R2R-PWM
FPGA-based 14bit DAC with resistance network and PWM.
FPGA-ftdi245fifo
FPGA-based USB fast communication using FT232H/FT600 chip.
gen_amba-1
AMBA bus generator including AXI, AHB, and APB
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
openwifi-hw
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
RiscSoC
RiscSoC 是一个芯片集成项目，包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成，部分 SoC 使用的自己设计的内核
SerialChart
一个很好用的串口示波器。
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
USTC-RVSoC
FPGA-based RISC-V CPU+SoC.
uvm-python
UVM 1.2 port to Python
uvm_verification
Examples with UVM
uvmprimer-1
Contains the code examples from The UVM Primer Book sorted by chapters.
UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
vnote
A pleasant note-taking platform.