Macsim

Introduction

MacSim is a heterogeneous architecture timing model simulator that is developed from Georgia Institute of Technology.
It simulates x86, ARM64, NVIDIA PTX and Intel GEN GPU instructions and can be configured as either a trace driven or execution-drive cycle level simulator. It models detailed mico-architectural behaviors, including pipeline stages, multi-threading, and memory systems.
MacSim is capable of simulating a variety of architectures, such as Intel's Sandy Bridge, Skylake (both CPUs and GPUs) and NVIDIA's Fermi. It can simulate homogeneous ISA multicore simulations as well as heterogeneous ISA multicore simulations. It also supports asymmetric multicore configurations (small cores + medium cores + big cores) and SMT or MT architectures as well.
Currently interconnection network model (based on IRIS) and power model (based on McPAT) are connected.
MacSim is also one of the components of SST, so multiple MacSim simulatore can run concurrently.
The project has been supported by Intel, NSF, Sandia National Lab.

If you're interested in the Intel's integrated GPU model in MacSim, please refer to intel_gpu branch.
We've developed a power model for GPU architecture using McPAT. Please refer to the following paper for more detailed information. Power Modeling for GPU Architecture using McPAT Modeling for GPU Architecture using McPAT.pdf) by Jieun Lim, Nagesh B. Lakshminarayana, Hyesoon Kim, William Song, Sudhakar Yalamanchili, Wonyong Sung, from Transactions on Design Automation of Electronic Systems (TODAES) Vol. 19, No. 3.
We've characterised the performance of Intel's integrated GPUs using MacSim. Please refer to the following paper for more detailed information. Performance Characterisation and Simulation of Intel's Integrated GPU Architecture (ISPASS'18)

Please see MacSim documentation file for more detailed descriptions.

git clone -b intel_gpu https://github.com/gthparch/macsim.git

download traces 
/macsim/tools/download_trace_files.py

./build.py --ramulator (please see /macsim/INSTALL)

Prof. Hyesoon Kim (Project Leader) at Georgia Tech Hparch research group (http://hparch.gatech.edu/people.hparch)

If you have a question, please use github issue ticket.

Here are two example configurations of SST+MacSim.
- A multi-socket system with cache coherence model:
- A CPU+GPU heterogeneous system with shared memory:

A heterogeneous architecture timing model simulator.

Language:C++ 76.0%Language:C 15.5%Language:Python 6.8%Language:Perl 1.0%Language:Makefile 0.6%Language:M4 0.1%Language:Shell 0.1%