growly

bfg

An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics

fpga_benchmarks

jsondotrulo

Generate graphviz DOT from Yosys's JSON output

date23_narrowing_the_gap

151_gf180mcu

BAG2_cds_ff_mpt

BAG2 workspace for fake PDK (cds_ff_mpt)

bfg_lut_test_sky130

bfg_mux_test_gf180mcu

blifdot

Generate graphviz DOT format from BLIF

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

cbag

A C++ VLSI circuit schematic and layout database library

CS50

Introduction to Computer Science exercises - CS50

dffram_lut

Standard Cell Library based Memory Compiler using DFF cells

hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

Hdl21

Hardware Description Library

lab3-252

Layout21

Integrated Circuit Layout

lut-tests

mqtt2prometheus

MQTT to Prometheus gateway

omgnutella

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

pyfive_top_202011

Top level for the November shuttle

tesla-osc

FPGA implementation of OSC control for tesla coils

venmo-pay

pay ski club for incredible shenanigans

Vlsir

Interchange formats for chip design.