gpthimble / quasiSoC

RISC-V SoC designed to be useful.

Quasi SoC

Crappy RISC-V CPU and fancy peripherals designed to be useful. Linux kernel capable. Free-software toolchain ready. Prioritize compatibility and easy-to-understand -- if I can write this, you also can.

∂CPU (partial CPU)

• Multiple-cycle RISC-V RV32IMA* Zicsr* @ 62.5 MHz, ~0.27 CoreMark/MHz
• M-mode, interrupt, exception*
  • Core local interrupt controller(CLINT, for mtime and software interrupt)
• Memory-mapped IO bus

   *: except amo(max|min)u?
   *: may not be exactly standard, stuffs like vectored interrupt not supported
   *: stuffs like illegal instruction not supported

Future plan

• Bus arbitration
• Platform-level interrupt controller(PLIC, for external interrupt)
• Sv32 MMU
• S-mode and U-mode
• GDB debug over openocd JTAG
• PMP (not planned)
• Formal verification (not planned)
• Pipeline (not planned)

Peripherals

• ESP-PSRAM64H as main memory, 8 MB, QPI mode @ 62.5 M, burst R/W
• Cache, direct mapping 32 KB(configurable) has bugs
• SDRAM (Easy but not before I get a better board)
• GPIO (LEDs, buttons, switches)
• UART (115200/921600/1843200 baud), boot from UART, rest from UART
• SD card (SPI mode, SDHC)
• PS/2 keyboard
• PS/2 mouse
• Graphics
  • HDMI, character terminal, frame buffer graphics(320x240 8-bit color, 640x480 2-bit monochrome)
    • Quality of life fixes
  • Old good VGA
  • ILI9486 320x480 LCD
    • Partial screen update
• CH375 USB disk
• W5500 ethernet module
• Bus converter: Use AXI/Wishbone peripherals
• Hart transplant: Use other RISC-V cores with my peripherals

Future plan

• Internet connectivity
  • LAN8720 ethernet module w/ RGMII (Hard)
  • ESP8266/ESP32 Wifi module (Boring)
  • lwIP? Need MAC + PHY(ENC28J60?) I guess...

Software

• Linux kernel 32-bit NOMMU uClibc
  • Drivers for my UART
  • Busybox "userspace"
• MicroPython port

Misc

• Standard RISC-V toolchain for RV32IM Newlib
• Basic RISC-V tests
• CoreMark performance approx. 0.27 CoreMark/MHz
• Fancy but very slow soft renderer

Boards & FPGAs

Xilinx 7 series

• xc7z010 PL @ SqueakyBoard, main dev platform ref
• xc7z020 PL @ PYNQ-Z1 w/ extension PMOD module ref
• xc7k325t @ Memblaze PBlaze 3 w/ extension board ref
• xc7a100t @ Nexys A7 on USTC FPGAOL, SW/LED/UART/UARTBOOT Instructions
• Xilinx 7-series w/ Symbiflow (partial)

Xilinx Spartan 6

• xc6slx16 @ Nameless LED controller module

Others

• ep4ce15 @ QMTech core board w/ SDRAM ref
• ep2c35 @ Cisco HWIC-3G-CDMA router module ref
• K210 or some other hardcore RISCV
• lfe5u or iCE40 w/ free software toolchain(Symbiflow, icestorm)

Build & Run

Quick start
Build & run instructions

Free-as-in-freedom
Free software toolchain -- SymbiFlow(Vivado-free!)

Linux Kernel

At least you saw a fancy kernel panic.
It's hacky, dirty, hard, and of no practical use

Alternative RISC-V Cores

Use other RISC-V cores with Quasi SoC peripherals. Currently supports PicoRV32.
Hart Transplant

Gallery

Linux kernel booting, init not ready yet, 8 MB RAM is enough for everything.

Pingo soft renderer of Viking room, with testing color strips, on HDMI monitor.

Ported MicroPython, on HDMI monitor.

CoreMark benchmarking, serial port.

Credits

Many peripherals' code are based on other's work. If I miss something please point out.

HDMI module, modified

HDMI module

SD card module, modified

UART module, heavily modified

Computer Organization and Design, where everything started

License

GPL-V3