[enhancement] IR/Verilog generation from parameterizable procs with Bazel rules
rw1nkler opened this issue · comments
What's hard to do? (limit 100 words)
Generating IR/Verilog out of a parameterizable proc is not possible when using Bazel rules
Current best alternative workaround (limit 100 words)
Currently, it is necessary to create a Proc that spawns a parameterizable proc with specific parameters. This Proc must then be passed to code generation (see #998 (comment))
However, since the wrapping Proc typically does not utilize channels (which are instead directly passed to the parameterized proc), the proc is usually removed during optimization. This results in either an almost empty Verilog module or issues with code generation. To address this problem, another workaround is required: marking the spawned proc as a top for the IR optimization step. This has been described in detail in #869 (comment)
Your view of the "best case XLS enhancement" (limit 100 words)
Expose attributes to specify parameters of the parameterizable procs in Bazel rules, and enable their usage by IR/Verilog generation tools. This can reduce the need for additional workarounds mentioned earlier without the need for proc-scoped channels that are under development. Even after introducing them, the proposed enhancement could be a valuable addition.
Related issues:
Thanks for reporting! As discussed in our April enhancement proposal review meeting: we're don't know the priority for this yet, but it's now on our list.