goodallen

goodallen

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DisplayPort

DisplayPort IP-core

Language:VerilogStargazers:37Issues:0Issues:0

ahb2apb-bridge

An uvm verification env for ahb2apb bridge

Language:SystemVerilogStargazers:42Issues:0Issues:0

EDID

EDID repository for LCD monitors

License:CC-BY-4.0Stargazers:285Issues:0Issues:0

forever-coolshell

酷壳 - CoolShell 电子存档,🕯️ 谨纪念和保存陈皓先生的公开的技术分享内容,感恩皓叔对中文互联网,尤其是技术领域无私的分享。

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core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

Language:VerilogStargazers:312Issues:0Issues:0

OpenSERDES

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Language:VerilogLicense:GPL-3.0Stargazers:127Issues:0Issues:0

FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

Language:HTMLLicense:MITStargazers:376Issues:0Issues:0

verilog-axis

Verilog AXI stream components for FPGA implementation

Language:PythonLicense:MITStargazers:674Issues:0Issues:0

verilog-axi

Verilog AXI components for FPGA implementation

Language:VerilogLicense:MITStargazers:1328Issues:0Issues:0

async_8b10b_encoder_decoder

Async 8b/10b enc/dec

Language:VHDLStargazers:9Issues:0Issues:0

dual-fisheye-video-stitching

Dual fisheye video stitching

Language:PythonLicense:MITStargazers:117Issues:0Issues:0

VideoStitchingViaShakinessRemoving

Demo code for our TIP video stitching paper in 2017

Language:MATLABLicense:BSD-2-ClauseStargazers:107Issues:0Issues:0

verilog_ppfifo_demo

Simple demo showing how to use the ping pong FIFO

Language:VerilogLicense:MITStargazers:14Issues:0Issues:0

OpenFPGA

An Open-source FPGA IP Generator

Language:VerilogLicense:MITStargazers:757Issues:0Issues:0
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Language:VHDLLicense:GPL-3.0Stargazers:2Issues:0Issues:0

ImageStitch

OpenCV图像拼接实现源码重构

Language:C++Stargazers:66Issues:0Issues:0

ImageStitchBasedOnFPGA

七路图像在FPGA中实现拼接,代码会不断添加进来。

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FPGA-Bicubic-interpolation

use Verilog HDL implemente bicubic interpolation in FPGA

Language:CoqLicense:GPL-3.0Stargazers:14Issues:0Issues:0

image-processing

SystemVerilog code for image processing tasks like demosaicing

Language:SystemVerilogLicense:NOASSERTIONStargazers:9Issues:0Issues:0

control-in-verilog

Template signal processing and control modules for FPGA.

Language:PythonLicense:MITStargazers:1Issues:0Issues:0

Elongate-BNN-demonstrator

Elongate technology demonstrator for zcu102 board using the binarized neural network

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xkISP

xkISP:Xinkai ISP IP Core (HLS)

Language:VerilogLicense:NOASSERTIONStargazers:214Issues:0Issues:0

Perception-based-seam-cutting

Our code for paper "perception-based seam cutting for image stitching"

Language:MATLABLicense:MITStargazers:21Issues:0Issues:0

NISwGSP

C++ implementation of the ECCV 2016 paper, Natural Image Stitching with the Global Similarity Prior.

Language:C++Stargazers:48Issues:0Issues:0

VideoStitch

Video Stiching with Opencv, MFC, SDL libraries

Language:C++Stargazers:21Issues:0Issues:0

Real-time-video-stitching

:telescope: This is a framework that combines multiple frames acquired from moving cameras

Language:C++Stargazers:115Issues:0Issues:0

StitchingVideo

this code is for stitching video in VC on opencv

Language:C++Stargazers:21Issues:0Issues:0