MLP simlator (+NeuroSim) V2.0
The MLP+NeuroSim framework was developed by Prof. Shimeng Yu's group (Arizona State University). The model is made publicly available on a non-commercial basis. Copyright of the model is maintained by the developers, and the model is distributed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International Public License
This is the released version 2.0 (May 1st, 2018) for the tool. Besides analog eNVM (in MLP simulator V1.0), this version also includes some new devices: SRAM, digital eNVM (RRAM, PCM and STT-MRAM) and FeFET, an optimized weight update scheme is introduced to reduce latency and energy in training.
For algorithm weights range extended from (0, 1) to (-1, 1) with more training algorithms (such as momentum method, Adagrad, RMSprop, and Adam), and digital eNVMs (e.g. STT-MRAM) based synaptic array with parallel read-out fashion, please go to released version 3.0 (Mar. 1st, 2019) MLP simulator (+NeuroSim) V3.0.
If you use the tool or adapt the tool in your work or publication, you are required to cite the following reference:
P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim+: An integrated device-to-algorithm framework for benchmarking synaptic devices and array architectures,§ IEEE International Electron Devices Meeting (IEDM), 2017, San Francisco, USA.
- MATLAB fitting script:
- Nonlinearity-to-A table:
- MNIST data:
- MLP Simulator (+NeuroSim): the rest of the files
Installation steps (Linux)
- Get the tool from GitHub
git clone https://github.com/neurosim/MLP_NeuroSim_2.0.git
MNIST_data.zipto it’s current directory
- Compile the codes
For the usage of this tool, please refer to the manual.
References related to this tool
- P.-Y. Chen, X. Peng, S. Yu, ※NeuroSim+: An Integrated Device-to-Algorithm Framework for Benchmarking Synaptic Devices and Array Architectures,*§ IEEE International Electron Devices Meeting (IEDM), 2017, San Francisco, USA.
- P.-Y. Chen, X. Peng, S. Yu, ※System-level benchmark of synaptic device characteristics for neuro-inspired computing,§ IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) 2017, San Francisco, USA.
- P.-Y. Chen, S. Yu, ※Partition SRAM and RRAM based synaptic arrays for neuro-inspired computing,§ IEEE International Symposium on Circuits and Systems (ISCAS), 2016, Montreal, Canada.
- P.-Y. Chen, B. Lin, I.-T. Wang, T.-H. Hou, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, and S. Yu, ※Mitigating effects of non-ideal synaptic device characteristics for on-chip learning,§ IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, Austin, TX, USA.
- P.-Y. Chen, D. Kadetotad, Z. Xu, A. Mohanty, B. Lin, J. Ye, S. Vrudhula, J.-S. Seo, Y. Cao, S. Yu, ※Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip,§ IEEE Design, Automation & Test in Europe (DATE), 2015, Grenoble, France.