Max's repositories
e203_hbirdv2
The Ultra-Low Power RISC-V Core
gitcyan.github.io
Build a Jekyll blog in minutes, without touching the command line.
pytools
useful Python scripts for learning and exercise
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
uvm-python
UVM 1.2 port to Python
XilinxTclStore
Xilinx Tcl Store
basic_verilog
Must-have verilog systemverilog modules
NyuziProcessor
GPGPU microprocessor architecture
nCovMemory
2020新冠肺炎记忆：报道、非虚构与个人叙述（持续更新） Memory of 2020 nCov: Media Coverage, Non-fiction Writings, and Individual Narratives (Continuously updating)
Gaia
Generate UVM testbench framework template files with Python 3
wujian100_open
IC design and development should be faster，simpler and more reliable
Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
UVMReference
Reference examples and short projects using UVM Methodology
uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
Bodh1.0
register auto generate from excel file
wavedrom
:ocean: Digital timing diagram rendering engine
uvm_tb_gen
generate UVM testbench using python
uvm-tutorial-for-candy-lovers
Source code repo for UVM Tutorial for Candy Lovers
SudokuPyWorks
A Sudoku game written in Python as an exercise miniproject for Python learning.
uvm_axi
uvm AXI BFM(bus functional model)