Giters
ghdl
/
ghdl-yosys-plugin
VHDL synthesis (based on ghdl)
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Stargazers:
298
Watchers:
40
Issues:
143
Forks:
32
ghdl/ghdl-yosys-plugin Issues
Wrongly assign the name internal signal for vhdl
Updated
2 months ago
Comments count
2
libgnat-13.so module missing
Closed
2 months ago
Comments count
2
GHDL+YOSYS formal verification, using Xilinx primitives
Updated
7 months ago
Comments count
1
Error when using plugin on M1 mac
Updated
8 months ago
Comments count
1
wire not found for $posedge
Updated
8 months ago
Comments count
3
Unable to build the plugin
Updated
9 months ago
Comments count
3
Another case of "wire not found for $posedge" - related to async resets?
Updated
9 months ago
Comments count
3
Please note that open-tool-forge/fpga-toolchain is no longer maintained
Closed
9 months ago
Comments count
1
The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).
Updated
10 months ago
The pre-built option #1 is extreamly outdated
Updated
10 months ago
Comments count
1
Upload of ghdl-yosys-plugin to Debian?
Closed
a year ago
Comments count
7
64 bits slicing problem
Closed
a year ago
Comments count
2
Unable to build plugin
Closed
a year ago
Comments count
30
ERROR: wire not found for $posedge
Updated
a year ago
Comments count
3
ECP5 Example fails: 'VLO' is unsupported
Closed
a year ago
Comments count
3
Failure to compile - ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
Closed
a year ago
Comments count
2
Error when using altera_mf lib
Updated
a year ago
Comments count
4
ERROR: No such command: ghdl (type 'help' for a command overview)
Closed
2 years ago
Comments count
5
Linking against libgnat-9.so.1
Closed
2 years ago
Comments count
10
Assertion error on synth-vhdl_expr.adb while importing entity into yosys
Closed
2 years ago
Comments count
3
error: clocked logic requires clocked logic on else part
Closed
2 years ago
Comments count
3
ERROR: wire not found for $posedge
Closed
2 years ago
Comments count
3
Error when using inout record
Updated
2 years ago
Comments count
3
Error with altera vendor libraries
Closed
2 years ago
Comments count
4
Improper sythesis with Yosis
Closed
2 years ago
make fails
Closed
3 years ago
Comments count
26
Use of BRAM in ICE40 ...
Updated
2 years ago
Comments count
2
High impedance assignment translates to 1'x
Updated
2 years ago
Comments count
6
VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names
Updated
2 years ago
Comments count
4
Error building ghdl plugin for yosys
Updated
2 years ago
Comments count
12
Roadmap for a release
Updated
2 years ago
Comments count
1
wire not found for $posedge
Updated
3 years ago
Comments count
3
Build library type mismatch
Closed
3 years ago
Comments count
24
make fails: unknown commands: "--libghdl-library-path" & "--libghdl-include-dir"
Closed
3 years ago
Comments count
40
ERROR: Assert `n.id != 0' failed - seems related to unassigned variables
Closed
3 years ago
Comments count
7
Yosys assert: is_fully_const() && GetSize(chunks_) <= 1 failed in kernel/rtlil.cc:4532
Closed
3 years ago
Comments count
2
Unable to synthesize large design
Closed
3 years ago
Comments count
2
GHDL VHDL support
Closed
3 years ago
Comments count
7
raised STORAGE_ERROR : stack overflow or erroneous memory access
Closed
3 years ago
Comments count
13
Support for 'keep' boolean attribute
Closed
3 years ago
Comments count
1
Case sensitivity issue
Closed
3 years ago
Comments count
8
Error: Info: No candidate top level module
Closed
3 years ago
Comments count
3
Add support for Yosys $live cell (needed for liveness proofs)
Updated
3 years ago
Comments count
2
ID::blackbox is not defined
Closed
3 years ago
Comments count
1
GHDL synthesis - beginner question
Closed
3 years ago
Comments count
3
RD_TRANSPARENT not set correctly for memories
Closed
3 years ago
Comments count
3
make fails
Closed
3 years ago
Comments count
3
Compilation broken
Closed
4 years ago
Comments count
5
mult18x18d component does not match yosys component
Closed
4 years ago
Comments count
2
GHDL synth internal state inconsistent with Yosys state
Updated
4 years ago
Comments count
6
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