Yonggang Liu's repositories
srsRAN
Open source SDR 4G/5G software suite from Software Radio Systems (SRS)
Cores-SweRVolf
FuseSoC-based SoC for SweRV EH1
Cores-SweRV
SweRV EH1 core
cfu_prjxray
for setup Symbiflow
prjxray
Documenting the Xilinx 7-series bit-stream format.
litex
Build your hardware, easily!
SpinalHDL
Scala based HDL
riscv-v-spec
Working draft of the proposed RISC-V V vector extension
digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
riscv-operating-system-mooc
《从头写一个RISC-V OS》课程配套的资源
rocket-chip
Rocket Chip Generator
snitch
Lean but mean RISC-V system!
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
rvv-llvm-project
PLCT实验室的 RISC-V V Spec 实现，基于llvm/llvm-project，rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8
3Dreconstruction
3D reconstruction, sfm with Python3
XiangShan
Open-source high-performance RISC-V processor
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
archbase
教科书《计算机体系结构基础》（胡伟武等，第三版）的开源版本
NutShell
RISC-V SoC designed by students in UCAS
SoftPipeline
简单的软光栅实现
caffe
Caffe: a fast open framework for deep learning.
tinyriscv
A very simple and easy to understand RISC-V core.
libyang
YANG data modeling language library
libnetconf2
C NETCONF library
www.chisel-lang.org
The home of the Chisel3 website
chisel-examples
Chisel examples and code snippets
shadowsocks-windows
A C# port of shadowsocks