Ganesan Chinnathambi's repositories
dynrama-sv
DYNamic RAndom Memory Allocator SystemVerilog Model
eight-queens-sv
Eight queens puzzle solver using SystemVerilog constraints.
open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
vutils_pkg
SV & UVM verification utilities
cheatsheets
Cheatsheats for various tools and languages
edgartools
Python library for working with SEC Edgar
MIT000
finpie
Simple library to download some financial data.
Language:PythonMIT000
pyutils
Useful, frequently used things for Python.
Language:Python000
tamil-utils
Tamil language utilities
Language:PythonMIT000
uvm_agent_gen
UVM Agent Generator
MIT000