FPGA_PSYC's repositories
clock-domain-crossing
In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.
Language:VHDL000
Flash-Controller
UT8QNF8M8 NOR Flash Controller VHDL Module
Language:VHDL000
FPGA_GigabitTx
Sending UDP packets out over a Gigabit PHY with an FPGA.
Language:VHDL000
verilog-ethernet
Verilog Ethernet components for FPGA implementation
Language:VerilogMIT000