fl4shk

libcheesevoyage

My SpinalHDL library intended to be reused across multiple HDL projects

flare_cpu

A 32-bit CPU being developed in SpinalHDL

gcc-snes

Port of the GNU Compiler Collection (and Binutils) to the Super Nintendo's various chips

volt64_console

Game Console for (tentatively) the DE0-CV (not tentatively) using Amaranth

frost64_console

A video game console being implemented in Amaranth

gcc-flare32

Flare32 port of GCC

liborangepower

Generic C++20 library consisting of mainly header files

binutils-gdb-flare

binutils-gdb-volt32

GNU Binutils backend for the Volt32 CPU

dunwich_sandgeon

Traditional Roguelike written in C++ using SDL2

fl4paint

FL4SHK's Paint Program (Geared Towards Sprites)

fling

(In Development) Compiled Programming Language with C Interop

fling_hdl

A Hardware Description Language with features similar to my custom programming language, Fling

pyhdlgen

A Python library for writing SystemVerilog code with a DSL.

SaveyBot

This is my re-implementation of https://github.com/Always8bit/SaveyBot/ in C++

sherwin_adventure_base

Sherwin's Adventure Base, the engine and some assets of Sherwin's Adventure, a platform game for modern systems

wfc

Wave Function Collapse in C++20

star_noise

(Incomplete) A Python library for generating an AST of a custom language, with SNES assembly and C code generation

antlr_to_recursive_descent

A tool for converting an LL(1) ANTLR-format grammar to my recursive descent parsing framework.

compute_snes_dma_time

fl4shk.github.io

ghdl

VHDL 2008/93/87 simulator

makefile_generation_stuff

Stuff for generating my GNU Makefiles using GNU m4

my_software_3d_renderer

Simple software 3D renderer written to be a reference for my FPGA-based 3D GPU

nmigen

A refreshed Python toolbox for building complex digital hardware

nmigen-boards

Board and connector definition files for nMigen

picolibc-flare32

picolibc - a C library designed for embedded 32- and 64- bit systems.

verilog_m4_extension

An extension to Verilog using the m4 macro processor and Python 3

volt64_cpu

Volt64 CPU, a fully Line Associative Registers-based CPU being implemented in the Amaranth HDL

yosys

Yosys Open SYnthesis Suite