The master device initiates the data communication by a start condition. The start condition is established by pulling the SDA from HIGH to LOW while the SCL stays HIGH.
The slave address is following the start condition for recognition use. For the SSD1306, the slave address is either "b0111100" or "b0111101" by changing the SA0 to LOW or HIGH.
The write mode is established by setting the R/W# bit to logic "0".
An acknowledgement signal will be generated after receiving one byte of data, including the slave address and the R/W# bit.
A control byte mainly consists of Co and D/C# bits following by six "0".
If the Co bit is set as logic "0", the transmission of the following information will contain data bytes only.
If the D/C# bit is set to logic "0", it defines the following data byte as a command. If the D/C# bit is set to logic "1", it defines the following data byte as a data which will be stored at the GDDRAM (Graphic Display Data RAM).
Acknowledge bit will be generated after receiving each control byte or data byte.
The write mode will be finished when a stop condition is applied. The stop condition is established by pulling the SDA in from LOW to HIGH while the SCL stays HIGH.
Which means, there are all four possible control bytes in the write mode for I2C:
Co
D/C#
Hex
Comment
Address Increment
0
0
0x00
Write command stream
No
0
1
0x40
Write data stream
Yes
1
0
0x80
Write single command
No
1
1
0xC0
Write single data
Yes
8.7 - Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 128 x 64 bits and the RAM is divided into eight pages, from PAGE0 to PAGE7, which are used for monochrome 128x64 dot matrix display.
When one data byte is written into GDDRAM, all the rows image data of the same page of the current column are filled. Data bit D0 is written into the top row, while data bit D7 is written into bottom row.
S S S S S
E E E E E
S S S S S G G G G G
E E E E E 1 1 1 1 1
G G G G G 2 2 2 2 2
0 1 2 3 4 3 4 5 6 7
+-+-+-+-+-+.........................................................+-+-+-+-+-+
D0 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D1 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D2 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D3 | | | | | | | | | | | |
PAGE0 +-+-+-+-+-+.........................................................+-+-+-+-+-+
D4 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D5 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D6 | | | | | | | | | | | |
+-+-+-+-+-+ +-+-+-+-+-+
D7 | | | | | | | | | | | |
+-+-+-+-+-+.........................................................+-+-+-+-+-+
Enlargement of GDDRAM
9 - Command Table
Fundamental Command Table
Hex
Command
0x81 + b^^^^^^^^
Set Contrast Control
0xA4 / 0xA5
Entire Display (RESET) ON
0xA6 / 0xA7
Set Normal / Inverse Display
0xAE / 0xAF
Set Display OFF / ON
Addressing Setting Command Table
Hex
Command
0x20 + b000000^^
Set Memory Addressing Mode (will use Horizontal Addressing Mode)
0x21 + b0^^^^^^^ + b0^^^^^^^
Set Column Address
0x22 + b00000^^^ + b00000^^^
Set Page Address
Hardware Configuration Command Table
Hex
Command
0x40 ~ 0x7F
Set Display Start Line
0xA0 / 0xA1
Set Segment Re-map
0xA8 + b00^^^^^^
Set Multiplex Ratio
0xC0 / 0xC8
Set COM Output Scan Direction
0xD3 + b00^^^^^^
Set Display Offset
0xDA + b00^^0010
Set COM Pins Hardware Configuration
Timing & Driving Scheme Setting Command Table
Hex
Command
0xD5 + b^^^^^^^^
Set Display Clock Divide Ratio / Oscillator Frequency
0xD9 + b^^^^^^^^
Set Pre-charge Period
0xDB + b0^^^0000
Set VCOMH Deselect Level
Software Configuration
Charge Bump Setting Command Table
Hex
Command
0x8D + b00010^00
Charge Pump Setting
Software Configuration
Below is an example of initialization flow of SSD1306.