fanhy2114 / Modeling-and-verification-of-a-multiprocessor-architecture-with-shared-memory

Protocol study, Components Modeling and Verification of specifications using NuSMV

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Modélisation

Définition des signaux d'interface des éléments de la plateforme, des interactions entre composants et de la nature des données à transférer

Automate de chaque composant

Bus

Arbitre

Mémoire

Cache L1

simplification hypothesis: the cache only transmits the queries

Processeur

In the code modelisation, I consider that the states WRITE and READ can be combined into one state

Snoop

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Protocol study, Components Modeling and Verification of specifications using NuSMV