DSI Core Readme ------------------------ 0. Disclaimer This project implements a MIPI DSI (MIPI Display Serial Interface) Verilog core. Since the DSI specification is non-public and requires an NDA, the core was built using bits and pieces available throughout the Web: presentations, display controller/SOC datasheets, various application notes and Android kernel drivers. The author is not associated in any way with the MIPI Alliance. The core is provided as-is, it has never been verified for compliance with the DSI standard and it probably lacks many of its features. You use it at your own risk, there's no warranty. 1. License - All HDL (unless otherwise noted) is released under LGPL v3.0 - All software (unless otherwise noted), is GPL v 3.0 or later. - PCB design and schematics are licensed under CERN Open Hardware License v 1.2. 2. Acknowledgements - Special thanks go to Sebastien Bourdeauducq, the creator of the Milkymist project, for his excellent IP cores (HPDMC, FML and LM32 Xilinx port) used by in the DSI shield firmware. - Andrew "Bunnie" Huang, for his EDID generation tools (Chumby WebTV project).