fabianschuiki

llhd

Low Level Hardware Description — A foundation for building hardware design tools.

moore

A hardware compiler based on LLHD and CIRCT

llhd-sim

The LLHD reference simulator.

superscalar-cpu

circt

Circuit IR Compilers and Tools

low

No fuss, just systems programming

bender

A dependency management tool for hardware projects.

sublime-riscv-assembly

RISC-V Assembly syntax for Sublime Text

env_logger

A logging implementation for `log` which is configured via an environment variable.

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

mlir

"Multi-Level Intermediate Representation" Compiler Infrastructure

morty

A SystemVerilog source file pickler.

phalanx

A Simulation Framework

pretty-env-logger

A pretty, easy-to-use logger for Rust.

sv-parser

SystemVerilog parser library fully complient with IEEE 1800-2017

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

btrfs-snapshot

A tool to create rotating btrfs subvolume snapshots

chisel

Chisel: A Modern Hardware Design Language

chisel-debug-tests

A collection of small standalone Chisel tests for debug info emission

configs

My personal collection of configuration and dotfiles

domain-types

firrtl

Flexible Intermediate Representation for RTL

fossi-foundation-web

fossi-foundation.github.io

FOSSi Foundation Website

frei0r

A large collection of free and portable video plugins

llvm-project

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.

mlt

MLT Multimedia Framework

package_control_channel

Default channel file for Package Control. Follow the directions at:

salsa

A generic framework for on-demand, incrementalized computation. Inspired by adapton, glimmer, and rustc's query system.

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.