ezchi / uvm-systemc

My local copy of UVM-SystemC

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UVM-SystemC Reference Implementation

About UVM-SystemC

The UVM-SystemC library provides an implementation of the Universal Verification Methodology (UVM) in SystemC/C++. The UVM-SystemC class library enables the development of scalable and reusable verification collateral for system-level verification and testing. The aim of UVM-SystemC is to be API compatible with UVM in SystemVerilog, to facilitate seamless integration and exchange of Verification IP (VIP) between system-level and IP-level test benches.

This version of UVM-SystemC is the reference implementation provided by the Accellera Systems Initiative and is developed by the SystemC Verification Working Group.


Licensing and Copyright

See the separate LICENSE and NOTICE files to determine your rights and responsiblities for using UVM-SystemC.

User Documentation

The main documentation of UVM-SystemC can be found in the docs directory. It contains the Language Reference Manual (LRM) and an introduction presentation.

Installation

See the separate INSTALL file that provides system information and installation instructions.

Release Notes

See the separate RELEASENOTES file that provides up-to-date information about this release of SystemC.

SystemC Verification Community


About Accellera SystemC Working Groups

Accellera's SystemC Working Groups are responsible for the definition and development of the SystemC Core and Transaction Level Modeling (TLM) language, including extensions for analog/mixed-signal (AMS), control, configuration, and inspection (CCI), sythesis and verification. Participants of these working groups include member companies and industry contributors. Technical contributors typically have many years of practical experience with IC and system-level design as well as developing system-level design methodologies and using EDA tools.

About Accellera Systems Initiative

Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership. Follow @accellera on Twitter or to comment, please use #accellera.

Accellera, Accellera Systems Initiative and SystemC are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.

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My local copy of UVM-SystemC

License:Apache License 2.0


Languages

Language:C++ 61.8%Language:Shell 21.7%Language:Makefile 14.9%Language:M4 0.7%Language:C 0.6%Language:CMake 0.3%