Exxcalibur

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

core-v-cores

CORE-V Family of RISC-V Cores

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

hw

RTL, Cmodel, and testbench for NVDLA

riscv-isa-sim

Spike, a RISC-V ISA Simulator

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

RV12

RISC-V CPU Core

chinese-poetry

The most comprehensive database of Chinese poetry 🧶最全中华古诗词数据库, 唐宋两朝近一万四千古诗人, 接近5.5万首唐诗加26万宋诗. 两宋时期1564位词人，21050首词。

verilog-axi

Verilog AXI components for FPGA implementation

basic_verilog

Must-have verilog systemverilog modules

fpu

synthesiseable ieee 754 floating point library in verilog

riscv-tests

rocket-chip

Rocket Chip Generator

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

1st-CLaaS

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

LF-Building-a-RISC-V-CPU-Core