evg-sin's starred repositories

stb

stb single-file public domain libraries for C/C++

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awesome-vscode

🎨 A curated list of delightful VS Code packages and resources.

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vlc

VLC media player - All pull requests are ignored, please use MRs on https://code.videolan.org/videolan/vlc

Language:CLicense:GPL-2.0Stargazers:13940Issues:581Issues:0

flipperzero-firmware

Flipper Zero firmware source code

Language:CLicense:GPL-3.0Stargazers:12630Issues:287Issues:1053

awesome-hpp

A curated list of awesome header-only C++ libraries

argcomplete

Python and tab completion, better together.

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Language:VerilogLicense:Apache-2.0Stargazers:1201Issues:38Issues:110

c-code-style

Recommended C code style and coding rules for standard C99 or later

Language:PythonLicense:MITStargazers:1026Issues:54Issues:6

libfastcommon

c common functions library extracted from my open source project FastDFS. this library is very simple and stable. functions including: string, logger, chain, hash, socket, ini file reader, base64 encode / decode, url encode / decode, fast timer, skiplist, object pool etc. detail info please see the c header files.

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Design-Patterns-in-C

Practical design patterns in C

Language:CLicense:MITStargazers:409Issues:30Issues:1

fpga_pio

An attempt to recreate the RP2040 PIO in an FPGA

Language:VerilogLicense:BSD-2-ClauseStargazers:289Issues:19Issues:5

switchboard

Communication framework for RTL simulation and emulation.

Language:PythonLicense:Apache-2.0Stargazers:255Issues:7Issues:56

awesome-dv

Awesome ASIC design verification

xk265

xk265:HEVC/H.265 Video Encoder IP Core (RTL)

minimax

Minimax: a Compressed-First, Microcoded RISC-V CPU

Language:VerilogLicense:BSD-3-ClauseStargazers:199Issues:10Issues:6

fxpmath

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

Language:PythonLicense:MITStargazers:180Issues:7Issues:74

FPGA-FixedPoint

A Verilog fixed-point lib: custom bit width, arithmetic, converting to float, with single cycle & pipeline version. 一个Verilog定点数库,提供算术运算、与浮点数的互相转换,包含单周期和流水线两种实现。

Language:VerilogLicense:GPL-3.0Stargazers:125Issues:5Issues:0

i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

Language:VerilogLicense:NOASSERTIONStargazers:105Issues:21Issues:38

FPGA-Gzip-compressor

FPGA-based GZIP (deflate) compressor. Input raw data and output standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据,输出标准的GZIP格式,即常见的 .gz / .tar.gz 文件的格式。

Language:VerilogLicense:GPL-3.0Stargazers:93Issues:4Issues:5

H264

H264视频解码verilog实现

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riscv-iommu

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

Language:SystemVerilogLicense:Apache-2.0Stargazers:73Issues:5Issues:27

PACoGen

PACoGen: Posit Arithmetic Core Generator

Language:VerilogLicense:BSD-3-ClauseStargazers:63Issues:5Issues:1

xkDLA

xkDLA:XinKai Deep Learning Accelerator (RTL)

Language:VerilogLicense:MITStargazers:25Issues:4Issues:0

nova

H.264/AVC Baseline Decoder

Language:VerilogStargazers:14Issues:0Issues:0

complex_multiplier

HDL code for a complex multiplier with AXI stream Interface

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Language:VerilogLicense:ISCStargazers:12Issues:4Issues:3
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