erjiaqing / MIPSmoothLatte

A MIPS Pipeline CPU, support add, addi, ori, lw, sw, j, beq

This repository is not active

A MIPS Pipeline CPU, support add, addi, ori, lw, sw, j, beq

Language:Verilog 64.1%Language:VHDL 28.9%Language:Coq 7.0%