First Activity on 3/3/2015
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This the repository for Degital II projects.
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Team members are :
- Eman H.Ahmed 900114948
- Abdelrahman El-Dallal 900115154
- Omar Khafagy 900115011
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The first project will be : Logic Circuit Schematic Beautifier
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Thursday 5/3/2015 (First Assesment)
The approach that our group will follow in the digital design project 1:
- Our proup will follow the Waterfall model while working on the project by which the progress will be flowing steadily downwards through the phases of conception, analysis, design, implementation, testing and maintanance.
- Now, we are in the conception and analysis phase.
- Throughout our research process, we could divide the project into three main parts:
- Reading a Verilog Gate Level Netlist and then converting it into a DAG.
- Applying a topological sorting algorithm on the constructed DAG.
- The output of applying the algorithm on the DAG will be used to identify the logical level of each gate.
- Research Process :
- We have been searching for more information about the Gate Level Netlist and how to convert it into a DAG conceptually. The materials we found about the Netlist was for course CS137: Electronic Design Automation at California Institute Of Technology. Also, we found extra material for the Gate Level Netlist at the MIT
opencourseware website for CS 6-884 Complex Digital Systems course. Here is the link : http://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-884-complex-digital-systems-spring-2005/lecture-notes/l05_synthesis.pdf - Also, we have been searching for the topological sorting algorithms and we found many resources that will be definitly beneficial throughout the project and especially at the stage of implementation.
http://www.personal.kent.edu/~rmuhamma/Algorithms/MyAlgorithms/GraphAlgor/topoSort.htm
http://homepage.cs.uiowa.edu/~hzhang/c19/ch11d.pdf http://courses.cs.washington.edu/courses/cse326/03wi/lectures/RaoLect20.pdf
- We have been searching for more information about the Gate Level Netlist and how to convert it into a DAG conceptually. The materials we found about the Netlist was for course CS137: Electronic Design Automation at California Institute Of Technology. Also, we found extra material for the Gate Level Netlist at the MIT
- The programming Language Used :
- We aren't still sure about which programming language we will use but most probably we will use matlab or Java.