This is a repository of the study "DL Compiler and Hardware". The goal of this study is to understand the acceleration of nerual networks with DL Compiler. The topic of acceleration includes Hardware-Aware Optimization,DL Compiler, TVM, ONNX , Compiler, PIM/CIM, NPU. Our study is based on recent papaers (Under recent two years). We discuss topics such as HW architecture, SW acceleration.
| When | Presenter | What | Links | Issue | Etc. |
|---|---|---|---|---|---|
| 7/5 | 박상수 | Introduction to Study & MTIA v1: Meta’s first-generation AI inference accelerator | #1 | #1 | - |
| 7/19 | - | - | - | #2 | - |
| 8/2 | 이민규 | Accelerating Personalized Recommendation with Cross-level Near-Memory Processing | - | #3 | - |
| 8/16 | 류재훈 | NNSmith: Generating Diverse and Valid Test Cases for Deep Learning Compilers | - | #4 | - |
| 8/30 | 김정현 | FACT: FFN-Attention Co-optimized Transformer Architecture with Eager Correlation Prediction | - | #5 | - |
| 9/13 | 이현승 | V10: Hardware-Assisted NPU Multi-tenancy for Improved Resource Utilization and Fairness | - | #6 | - |
| 9/27 | 유준봉 | GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks | - | #7 | - |
| 10/11 | 설광수 | TBD | - | #8 | - |
| 10/25 | - | - | - | #9 | - |
| 11/08 | - | - | - | #10 | - |
| 11/22 | - | - | - | #11 | - |
| 12/6 | - | - | - | #12 | - |
| 12/20 | - | - | - | #13 | - |
| 1/10 | - | - | - | #14 | - |