ekiwi

wellen

wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.

rtl-repair

Fast Symbolic Repair of Hardware Design Code

simulator-independent-coverage

Project Repo for the Simulator Independent Coverage Research

fst-native

Native Rust implementation of the FST waveform format from GTKWave.

baa

BitVector and Array Arithmetic library

patronus

work in progress, playing around with btor2 in rust

chisel-sequences

sequence prototype

calyx

Intermediate Language (IL) for Hardware Accelerator Generators

ekiwi.github.io

essent

high-performance RTL simulator

firesim

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

firrtl2

UC Berkeley Copy of the FIRRTL Compiler

hardware-bugbase

hwmcc20

Hardware Model Checking Competition 2020 Benchmarks and Results

ip-contributions

For contributions of Chisel IP to the chisel community.

aws-fpga-firesim

AWS Shell for FireSim

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

chisel-pla

chisel-template

A template project for beginning new Chisel work

chisel-testers2

Repository for chisel3 testers2 open alpha

easy-smt

Easy SMT solver interaction

ffi_benchmarks

firrtl

Flexible Intermediate Representation for RTL

firrtl-spec

The specification for the FIRRTL language

hwmcc19

Hardware Model Checking Competition 2019 Benchmark Data

latency-insensitive-interface-combinators-in-chisel

Chisel implementation of Latency-Insensitive Interface Combinators. Based on: https://dl.acm.org/doi/10.1145/3575693.3575701

metalift

A program synthesis framework for verified lifting applications

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

tt02-tweezers

Submission template for TT02

verilog-coverage

Trying to implement simple coverage metrics for Verilog.