Reliability of the result

[Anderson Ignacio]

Hey,

I have been running CoreMark with a simple RISC-V 32-bit core single issue in-order pipeline and the results are quite impressive as it shown below. When comparing with other cores it seems that this one outperform most of the others which does not make much sense due its simple microarchitecture when in comparison with designs like Aria/CV32E40P. What are the places to check if the CoreMark port for this architecture is correct or not?

2K performance run parameters for coremark.
CoreMark Size    : 666
Total ticks      : 667898007
Total time (secs): 13
Iterations/Sec   : 230
Iterations       : 3000
Compiler version : riscv-none-embed-gcc (xPack GNU RISC-V Embedded GCC x86_64) 10.2.0
Compiler flags   : -O0 -g -march=rv32i -mabi=ilp32 -Wall -Wno-unused -ffreestanding --specs=nano.specs -DPRINTF_DISABLE_SUPPORT_FLOAT -DPRINTF_DISABLE_SUPPORT_EXPONENTIAL -DPRINTF_DISABLE_SUPPORT_LONG_LONG -DREAL_UART -Wall -Wno-main -DPERFORMANCE_RUN=1  -O0 -g
Memory location  : STACK
seedcrc          : 0xe9f5
[0]crclist       : 0xe714
[0]crcmatrix     : 0x1fd7
[0]crcstate      : 0x8e3a
[0]crcfinal      : 0xcc42
Correct operation validated. See README.md for run and reporting rules.

In the core_portme.c I am using this

CORETIMETYPE cpu_get_cycle(void) {

  union {
    uint64_t uint64;
    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
  } cycles;

  register uint32_t tmp1, tmp2, tmp3;
  while(1) {
    tmp1 = read_csr(0xC80);
    tmp2 = read_csr(0xC00);
    tmp3 = read_csr(0xC80);
    if (tmp1 == tmp3) {
      break;
    }
  }

  cycles.uint32[0] = tmp2;
  cycles.uint32[1] = tmp3;

  return cycles.uint64;
}
/* Define : TIMER_RES_DIVIDER
        Divider to trade off timer resolution and total time that can be
   measured.

        Use lower values to increase resolution, but make sure that overflow
   does not occur. If there are issues with the return value overflowing,
   increase this value.
        */
#define CLOCKS_PER_SEC             50000000
#define GETMYTIME(_t)              (*_t = cpu_get_cycle())
#define MYTIMEDIFF(fin, ini)       ((fin) - (ini))
#define TIMER_RES_DIVIDER          1
#define SAMPLE_TIME_IMPLEMENTATION 1
#define EE_TICKS_PER_SEC           (CLOCKS_PER_SEC / TIMER_RES_DIVIDER)

[Peter Torelli]

There's not much to port, just the timer as you've done. If you can confirm that the timer is properly configured, and if the CRCs are correct, there's not much else to be done.