Construct a single-cycle RISC-V CPU with Chisel
Warning
Please be aware that the Scala code in this repository is not entirely complete, as the instructor has omitted certain sections for students to work on independently.
Development Objectives
Our goal is to create a RISC-V CPU that prioritizes simplicity while assuming a foundational understanding of digital circuits and the C programming language among its readers. The CPU should strike a balance between simplicity and sophistication, and we intend to maximize its functionality. This project encompasses the following key aspects, which will be prominently featured in the technical report:
- Implementation in Chisel.
- RV32I instruction set support.
- Execution of programs compiled from the C programming language.