Harmonica SIMD Architecture implementation in SystemVerilog. This is the initial version of the RTL. The doc directory has the documentation of the RTL project. Enjoy!
To run the Harmonica RTL Project: TODO: Direction using free RTL compilers (Verilator?) and waveviewer (GTKWave?)
- SSH to ecelinsrvx.ece.gatech.edu
- source /tools/mentor/modelsim/ms106a/cshrc.modelsim
- vsim &
- File -> New -> Project (Enter a project name and press OK)
- Add Existing File (Add all of the *.sv file from the src directory)
- Compile -> Compile All
- VSIM 2 > do ../scripts/sig_gen
- Remove all signals from the waveform
- VSIM 2 > do ../scripts/sig_debug
- Look at the generated tracker files and waveform.