dzwduan / cache-simulator

Cache Simulator

Prefetch design

Instruction prefetch

• Next-Line Prefetching
• Fetch-Directed Prefetching
• Discontinuity Prefetching
• Prescient Fetch
• Temporal Instruction Fetch Streaming
• Return-Address Stack-Directed Instruction Prefetching
• Proactive Instruction Fetch

Data prefetch

• Stride Prefetcher
• Stream Prefetcher

...

Optimization

• way prediction
• multi bank
• MSHR
• critical word first
• early restart
• write merging
• compiler
• coherence

Basic

• fully-associative
• set-associative
• direct-mapped
• write through + non-write allocate
• write back + write allocate (add dirty bit)
• victim cache
• PIPT
• VIPT

run

1. simple cache test with LRU, trace refer here

make clean
make simple-run

Testing

Once you have created the binary, you can run it with the following command: bunzip2 -kc trace.bz2 | ./cache <options> The options are as follows:

  --help                     Print this message
  --icache=sets:assoc:blocksize:hit    I-cache Parameters
  --dcache=sets:assoc:blocksize:hit    D-cache Parameters
  --l2cache=sets:assoc:blocksize:hit   L2-cache Parameters
  --inclusive                Makes L2-cache be inclusive
  --prefetch                 Enable Prefetching
  --memspeed=latency         Latency to Main Memory

The testing can be done using the traces given to you in the repository. There are 2 correct outputs given for 2 configurations as follows:

1. MIPS R10K - Reference Manual:

   • I$: 32KB, 2-way, 2 cycles hit latency
   • D$: 32KB, 4-way, 2 cycles hit latency
   • L2: 128KB, 8-way, off-chip, 50 cycles hit latency
   • 128B block size
   • ./cache --icache=128:2:128:2 --dcache=64:4:128:2 --l2cache=128:8:128:50 --memspeed=100

2. Alpha A21264 - Reference Manual:

   • I$: 64KB, 2-way, 2 cycles hit latency
   • D$: 64KB, 4-way, 2 cycles hit latency
   • L2: 8MB, 8-way, off-chip, 50 cycles hit latency
   • 64B block size
   • ./cache --icache=512:2:64:2 --dcache=256:4:64:2 --l2cache=16384:8:64:50 --memspeed=100

3. Open Xiangshan - Reference Manual:

   • TODO

Refer

1. trace from ECE447 + CSE240A + ECE563
2. CacheMemory
3. A Primer on Memory Consistency and Cache Coherence
4. A Primer on Hardware Prefetching
5. The 3rd Data Prefetching Championship
6. Computer Architecture: A Quantitative Approach (Sixth Edition) CH2 + Appendix B
7. cache tutorial
8. cache test
9. NJU slides