Single Cycle CPU for MIPS
Support the instructions below:
add
sub
and
or
srl
addi
andi
ori
lw
lui
sw
slt
slti
beq
bne
j
jal
jr
nor
sll
xor
xori
jarl
Multi-Cycle CPU for MIPS
Support the instructions above.
The Project for course
MicroProgramming for Multi-Cycle CPU