dpetrisko

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi_mem_if

Simple single-port AXI memory interface

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

bp-yocto

bsg_adder

bsg_bladerunner

Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)

bsg_bp_nocs_paper

bsg_fifo_divide

bsg_replicant

Bespoke Silicon Group AWS EC2 F1 Infrastructure and Interface logic for BSG Manycore

bsg_sv2v

dma_ip_drivers

fossi-foundation.github.io

FOSSi Foundation Website

hb_miniblade

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

openc910

OpenXuantie - OpenC910 Core

openpiton

The OpenPiton Platform

OpenRAM

An open-source static random access memory (SRAM) compiler.

opentitan

OpenTitan: Open source silicon root of trust

riscv-arch-test

riscv-dv

riscv-gcc

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

riscv-opcodes

RISC-V Opcodes

rocket-chip

Rocket Chip Generator

skywater-pdk-libs-sky130_fd_sc_hd

"High density" digital standard cells for SKY130 provided by SkyWater.

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

test-repo

verilator

Verilator open-source SystemVerilog simulator and lint system