doudouli12's repositories
AHB-SRAMC
IC Verification & SV Demo
AHB-to-APB-Bridge-Verification
Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
ahb2apb-bridge
An uvm verification env for ahb2apb bridge
ALU-Verification-Environment
Development UVM Verification Environment for ALU DUT
apb_vip
Verification IP for APB protocol
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi4_vip
Verification IP for APB protocol
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cpu8080-alu
UVM code to verify ALU
FIFO_verification-
fifo verification IP using system verilog
i2c_vip
Verification IP for I2C protocol
LM-RISCV-DV
An Open-Source Design and Verification Environment for RISC-V
MPSoC-DV
MPSoC verified with UVM/OSVVM/FV
opentitan
OpenTitan: Open source silicon root of trust
PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
Python
My Python Examples
Python-100-Days
Python - 100天从新手到大师
Python_1
Python3编写的各种大小程序，包含从零学Python系列、12306抢票、省市区地址库以及系列网站爬虫等学习源码
riscv
RISC-V CPU Core (RV32IM)
riscv-formal
RISC-V Formal Verification Framework
riscv-vip
For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
SoC-DV
System on Chip verified with UVM/OSVVM/FV
timer_verification_ip
This repository contains a Verification IP for the timer. This VIP tests the timer by applying constrained random stimulus. Sequences of transactions reset, configure the timer, and perform read & write operations on the respective registers of the timer.
uart2bustestbench
UVM Verification IP to uart2bus IP.
uvm_tb_cross_bar
SystemVerilog UVM testbench example
verilog-axi
Verilog AXI components for FPGA implementation
wbuart32
A simple, basic, formally verified UART controller
wujian100_open
IC design and development should be faster，simpler and more reliable