Dinesh Kumar's repositories
Carry-Look-Ahead-Adder-MAGIC-layout
Layout of a Carry Look-Ahead Adder using MAGIC VLSI along with extracted SPICE file
Carry-look-ahead-adder-Verilog
Implementation of a Carry look-ahead adder (CLA) using Verilog
Language:Verilog000
Language:MATLAB000
hacktoberfest
Hacktoberfest Hyderabad Repo
Language:C000
ILSBB
It's Like Splitwise, But Better
Language:HTML000
Language:PythonGPL-3.0000
Language:JavaScriptGPL-3.0000
GPL-3.0000
Language:C++000
Language:Jupyter NotebookMIT000
Language:PythonGPL-3.0000
y86_processor
A Y86 processor built and simulated on Verilog HDL
Language:Verilog000