DeltaEqual0

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

i2c_draft_gsoc

A simple low power I2c slave, this is just a prototype

VeeRwolf

FuseSoC-based SoC for VeeR EH1 and EL2

carbonyl

Chromium running inside your terminal

rocket-chip

Rocket Chip Generator

zju-icicles

浙江大学课程攻略共享计划

SpaceEye

Live geostationary weather satellite imagery for your desktop background

PVS464

i3wm-themer

🎨 Theme collection manager for i3-wm

caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

ArchLinuxTutorial

✨Arch Linux安装使用教程 每日实时更新！ | 包含ArchLinux从安装到日常使用、娱乐、编程、媒体制作的各个方面，让Arch成为你的常用系统吧！ | 提供在线网页文档 ✨

e203_hbirdv2

The Ultra-Low Power RISC-V Core

XiangShan

Open-source high-performance RISC-V processor

cdsgit

Cadence Virtuoso Git Integration written in SKILL++

libsnark

C++ library for zkSNARKs

awesome-zero-knowledge-proofs

A curated list of awesome things related to learning Zero-Knowledge Proofs (ZKP).

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

ElegantNote

Elegant LaTeX Template for Notes

NutShell

RISC-V SoC designed by students in UCAS

buy-all-steam-games

see how much does it cost to buy all steam games

Learn-Vim

Learning Vim and Vimscript doesn't have to be hard. This is the guide that you're looking for 📖

yosys

Yosys Open SYnthesis Suite

opentitan

OpenTitan: Open source silicon root of trust

ish

Linux shell for iOS

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

apb_i2c

COVID-19

Novel Coronavirus (COVID-19) Cases, provided by JHU CSSE

Cores-VeeR-EH1

VeeR EH1 core

parallella-riscv

RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards