deilt's repositories
basic_verilog
Must-have verilog systemverilog modules
verilog-axis
Verilog AXI stream components for FPGA implementation
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
chatgpt_academic
科研工作专用ChatGPT拓展，特别优化学术Paper润色体验，支持自定义快捷按钮，支持markdown表格显示，Tex公式双显示，代码显示功能完善，新增本地Python工程剖析功能/自我剖析功能
CPlusPlusThings
C++那些事
Cpp-Primer-Plus-6th
《C++ Primer Plus 第6版（中文版）》原书代码、习题答案和个人笔记，仅供学习和交流。
Cpp_Primer_Answers
《C++ Primer》第五版中文版习题答案
Cpp_Primer_Practice
搞定C++:punch:。C++ Primer 中文版第5版学习仓库，包括笔记和课后练习答案。
GitHub520
:kissing_heart: 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）
HDL-Bits-Solutions
This is a repository containing solutions to the problem statements given in HDL Bits website.
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
missing-semester-cn.github.io
the CS missing semester Chinese version
MPSoC-DV
Multi-Processor System on Chip verified with UVM/OSVVM/FV
oh_ip
Verilog library for ASIC and FPGA designers
opentitan
OpenTitan: Open source silicon root of trust
📚 计算机经典编程书籍、大黑书、编程电子书、电子书、编程书籍，包括计算机基础、C/C++、Java、Python、面试题、架构设计、算法系列等经典电子书。
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
rvcc-env-docker
Dockerfile for the RVCC course
verilog-axi
Verilog AXI components for FPGA implementation
zotero-pdf-translate
PDF translation add-on for Zotero 6
ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.