Deepware's repositories
MMM_SA_2by2_posit_4_0
This repository contains a Matrix-Matrix-Multiply unit performed by a 2x2 systolic array and posit<4,0> numbers
libposit
A library for working with the posit number type.
OpenCLue
Accel Demos
soDLA
Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
NPU-Simulator
C++ Simulator for Neural Processing Unit
Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
EE577b-Course-Project
awesome-edge-machine-learning
A curated list of awesome edge machine learning resources, including research papers, inference engines, challenges, books, meetups and others.
vmware-verilog-jit-compiler-cascade
A Just-In-Time Compiler for Verilog from VMware Research
Deep-Neural-Network-Hardware-Accelerator-1
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
NACU
This is a repository for the "NACU: A Non-Linear Arithmetic Unit for Neural Networks"
CMix-NN
CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices
gemm_array
Basic Implementations of a 1-D GEMM Systolic Array
transpyle
HPC-oriented transpiler for C, C++, Cython, Fortran, OpenCL and Python.
esp-chisel-accelerators
Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
nocgen
NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
bismo
BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
FPGA-Systolic-DMMM
Dense matrix-matrix multiplication for acceleration with FPGA on AWS F1 instance
somnia
Learn NVDLA by SOMNIA
nvgen
NVDLA generator, aiming to optimize the design agility and hardware performance.
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
XJTU-Tripler
XJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
Deep-Neural-Network-Hardware-Accelerator
My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket
SimpleTPU
A FPGA Based CNN accelerator, following Google's TPU V1.
Zynq-7000-DPU-TRD
Zynq-7000 DPU TRD
MARLANN
Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
Q-MANN
Quantized Memory-Augmented Neural Networks (AAAI-18)
Configurable-Systolic-Systemverilog
Systolic Implementation