• Built a tool that flexibly generates hardware to accelerate the evaluation of multiple layers of convolution system with a non-linear function called a ReLU after each convolution • Designed it using digital system design techniques such as control module, data path and FSM • Enhanced the speed by adding parallelism and pipelining • Programmed the tool by C++ for software development and System Verilog to generate the hardware • Tested the tool by using random testbenches for its speed, area, throughput and energy consumption
This repository contains my digital design projects. Each folder contains the problem statement and the reports for the projects. The projects are in System Verilog codes for ASIC design. Refer Project Handouts for detailed descriptions.
Project 1: Multiply Accumulate Hardware >> Project Handout
Project 2: Matrix Vector Multiplication Hardware >> Project Handout | Project Report
Project 3: Accelerated Hardware Generation Hardware >> Project Handout | Project Report
• Built a tool that flexibly generates hardware to accelerate the evaluation of multiple layers of convolution system with a non-linear function called a ReLU after each convolution • Designed it using digital system design techniques such as control module, data path and FSM • Enhanced the speed by adding parallelism and pipelining • Programmed the tool by C++ for software development and System Verilog to generate the hardware • Tested the tool by using random testbenches for its speed, area, throughput and energy consumption