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dea1ka

dea1ka

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jTDC

FPGA based 30ps RMS TDCs

Language:VHDLLicense:GPL-3.0Stargazers:72Issues:0Issues:0

TDC

Verilog implementation of a tapped delay line TDC

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CYCLONE_IV_EP4CE15

Stargazers:23Issues:0Issues:0